Among the advances sought by designers of read-only memories are features which increase the data storage density while reducing or at least maintaining the access time. In attempting to obtain such objectives, contemporary designers of ROMs, utilizing silicon gate field effect transistors (FETs) programmed by the selective formation of depletion or enhancement devices, have digressed from the common NOR/OR logic arrangements toward the higher densities inherent with NAND/AND logic arrangements. The distinctions and considerations which result in the trend are aptly described in U.S. Pat. No. 4,142,176, the subject matter of which is hereby incorporated by reference.
FIGS. 1 and 2 illustrate the general state of the present technology as it relates to NAND configurations of FETs to form ROM arrays. In the rudimentary NAND ROM, 1, illustrated in FIG. 1, lines designated ROW 0 to ROW n are selectively energized with binary "0" or "1" level voltages, 0 and 5 volts respectively, while BIT LINES 0 to m are selectively monitored for a ground path as the response. If, as shown in FIG. 1, FET 2 is fabricated to be a depletion type device, the output on BIT LINE m-1 is the same whether the voltage on the line of ROW 3 is a "0" or a "1". The efficiency with which such a configuration utilizes available chip area is also described in the aforementioned U.S. Patent.
Notwithstanding the improved density obtained with the configuration represented by the NAND ROM 1, its usage is relatively limited by virtue of the slow access speed. In comparison, the access speed is significantly worse than that of a classic NOR configured ROM. The slow speed is primarily a result of the longer path length, and associated increase in the path impedance.
In an attempt to balance the design characteristics optimizing density and those favoring access time, it has been proposed that the logic arrangement of the ROM take the NAND ROM WITH BANK (stack) SELECT configuration shown at 3 in FIG. 2. With this configuration additional bit lines, such as 4, divide the n row array into two banks to reduce the length of the series path through the NAND FETs by approximately one-half. In exchange, the ROM sacrifices the chip area consumed by the additional bit lines; additional bank select addressing FETs, such as FETs 6 and 7; and additional connections 8 to join line 4 with the electrode corresponding to node 9. Common practice prescribes that node 9 actually constitute a single source/drain (S/D) diffusion, common to FETs 6 and 7, that line 8 be a via through a dielectric layer, and that line 4 be a second conductive (metal) layer physically situated substantially overlying the corresponding columns of FETs. The first conductive layer in such an integrated circuit configuration is typically patterned from the polycrystalline silicon (poly) to form the FET gate electrodes corresponding to the row and bank select lines.
Unfortunately, NAND ROM WITH BANK SELECT 3 requires a significant sacrifice in chip density to decrease the access time. To understand the relative implications of density, contrast the logic arrangements in FIGS. 1 and 2 in terms of integrated circuit structure. Given that the number of rows is relatively large, the loss in chip area due to nodes 9, connecting lines 8, and bank select FETs 6 and 7, in progressing from the single NAND ROM in FIG. 1 to the NAND ROM WITH BANK SELECT in FIG. 2, is minimal. To some extent this result is attributable to the continuity of the small pitch (spacing from center-line to center-line) between the row-oriented poly gate lines. The columns in the configuration of FIG. 2 are, however, significantly affected by the structural rearrangement. Though the pitch between successive diffusions defining the columns of FETs remains unaltered, the larger pitch of the bit lines now imposes a lower limit on the spacing between successive columns. For example, if the active area pitch, i.e., the pitch of the diffusion forming the successive bit lines m-1, m of the NAND ROM configuration in FIG. 1, were nominally 4 microns, and the nominal pitch of the metal bit lines 4 in the NAND ROM WITH BANK SELECT of FIG. 2 were 8 microns, the metal bit lines would constrain the ROM density to approximately one-half that available with the configuration in FIG. 1.